Optimizing a digital circuit at a transistor level may often be more difficult than optimizing an analog circuit because of the electrical parameters of a MOS or CMOS transistor such as gate capacitance and drain current which depend strongly on a transistor's terminal voltages and which in turn change rapidly with time in a digital circuit. Further, a particular charging or discharging path and the various load capacitances may look very different for different logic states that the circuit may be in. Current prescaler systems may have dynamic flip flops in dividers that fail to provide a usable output signal that will drive a subsequent stage, particularly at environmental and process extremes. Current prescaler systems may also have prescaler circuits that require additional drive from a buffer amplifier and represent additional parasitic capacitance within the prescaler circuit that prevents the prescaler circuit from operating at higher frequencies. Thus, a need exists for divider circuits and prescaler circuits within a prescaler system that can operate at environmental extremes and at higher frequencies (and/or broader frequency ranges) and that further overcome the problems described above.